DATA
TECHNICAL
CPU
High-performance core solo ARM Cortex A9 processor
Mechanism of providing dual-core services, processing capability of 2500 MIPs
Built-in I-cache, D-cache, and L2 cache
Hardware JAVA acceleration
Floating-point coprocessor
Memory Control Interface
Double-data rate 2 (DDR2)/DDR3 interface
Maximum memory of 1 GB
32-
bit memory width
Serial peripheral interface (SPI) flash
NAND flash
Video Decoding
H264 MP, HP@ level 4.1
MPEG1
MPEG2 MP@HL
MPEG4 SP@ levels 0–3 and ASP@ levels 0–5
MPEG4 short header format (H.263 baseline)
Divx4–6
AVS baseline@ level 6.0
H.263
RealVideo8/9/10
VC-1 AP
Decoding capabilities of 1080p (30 fps) and 576i (25 fps) or 480i (30 fps)
Video post-processing such as denoising and deblocking Picture Decoding
Full high-definition JPEG decoding, a maximum of 64 megapixels
PNG decoding, a maximum of 64 megapixels
Audio/Video Encoding
H.264/MPEG-4 video encoding, a maximum of 720x576@25 fps
JPEG encoding
Variable bit rate (VBR) and constant bit rate (CBR) modes for video encoding
1-
channel audio encoding
Echo cancellation
Audio Decoding
MPEG L1/L2 decoding
Dolby digital and Dolby digital plus decoding
AC3 transparent transmission
Down mixing
Resampling
2-
channnel sound mixing
Intelligent volume control
TS Demultiplexing/PVR
3-
channel transport stream (TS) inputs including 1-channel intermediate
frequency (IF) input
One built-in quadrature amplitude modulation (QAM) module
1-
channel QAM loopback output
A maximum of 96 packet ID (PID) filters
Full-service personal video recorder (PVR)
Recording of scrambled and non-scrambled streams
Advanced encryption standard (AES), data encryption standard (DES),
or triple data encryption standard (3DES) data encryption
Content protection for universal serial bus (USB) devices
+
Vitor Martins Augusto
TELE-satellite
Test Center
Portugal
Content protection for serial advanced technology attachment (SATA) or external
serial advanced technology attachment (eSATA) hard disks
Security Processing
Advanced security features
One-time programmable (OTP) and chip ID Graphics Processing
Enhanced full-hardware 2D graphics acceleration engine
Full-hardware anti-aliasing and anti-flicker
Full-hardware 3D graphics processing unit (GPU) acceleration engine
Standard OpenGL ES 2.0/1.1/1.0 OpenVG 1.1 interfaces
Display Processing
2-
layer on-screen display (OSD)
16-
bit or 32-bit color depth
Two background layers and two video layers
1920-
pixel width for each layer
Image enhancement
Audio/Video Interface
Output norm of PAL, NTSC, or SECAM and force standard
conversion
Aspect ratio of 4:3 or 16:9, force aspect ratio conversion, and scaling
1080
p 50(60)/1080i/720p/576p/576i/480p/480i outputs
Receiving of standard-definition and high-definition signals
Simultaneous output of high-definition and standard-definition signals from the
same source or different sources
xvYCC (IEC 61966-2-4) standard for color gamut
Digital video interface
High-definition multimedia interface 1.4 (HDMI 1.4) with high-bandwidth
digital content protection 1.2 (HDCP 1.2)
One BT.656/601 or BT.1120 video input (VI) interface
One 24-bit red-green-blue (RGB) output interface
Analog video interface
One composite video broadcast signal (CVBS) interface
One YPrPb interface
One S-Video interface
Six built-in video digital-to-analog converters (DACs)
Configurable output interface
Macrovision and vertical blanking interval (VBI)
Audio interface
Left-audio and right-audio channels (RCA output interface with
low impedance and imbalance)
Sony/Philips digital interface (SPDIF)
One built-in audio DAC
One digital audio input/audio output (AI/AO) interface
(
pulse code modulation (PCM) with multiple time slots)
Peripheral Interface
One eSATA/SATA interface (with integrated physical layer (PHY)),
supporting 1.5 Gbit/s or 3.0 Gbit/s rate
One peripheral component interconnect express (PCIe) interface (with integrated PHY)
Two USB 2.0 host ports (with integrated PHY)
One 8-bit secure digital input/output (SDIO) interface
Two 10/100 Mbit/s adaptive Ethernet ports supporting the 2-layer or 3-layer switch
function or one 10/100 Mbit/s or 10/100/1000 Mbit/s adaptive Ethernet port
Three universal asynchronous receiver transmitter (UART) interfaces
Two smart card interfaces, supporting T0, T1, and T14 protocols
One infrared (IR) receiver processor and two input interfaces
One light emitting diode (LED) and keypad control interface
Three inter-integrated circuit (I2C) interfaces
13
groups of general-purpose input/output (GPIO) interfaces
Others
Fast startup
Downloading and running of boot programs through the serial port
Passive standby and low-power consumption
Entire standby power less than 1 W
Typical entire power less than 9 W in operating mode
756-
pin plastic ball grid array (PBGA) package with 31 mm x 31 mm dimensions
and 0.8 mm pitch
177
www.TELE-satellite.com
—
1 -12/2012 —
TELE-satellite International —
全球发行量最大的数字电视杂志
SoC with ARM Cortex A9 and possibility to
integrate digital tuners
Open Source
Android 4.x support
All current interfaces and connections pos-
sible
Low power consumption
The IP address can not be changed using NMS
Expert Opinion